Tushar Krishna

Biography

Tushar Krishna is an Associate Professor in the School of Electrical & Computer Engineering at Georgia Tech, with a courtesy appointment in Computer Science. His research spans computer architecture, interconnection networks, networks-on-chip, and AI/ML accelerator systems — with a focus on optimizing data movement in modern computing platforms.

He held the ON Semiconductor (Endowed) Junior Professorship in ECE from 2019–2021, and has been a visiting professor at MIT EECS + CSAIL and Harvard CS, and a researcher in Intel's VSSAD group. He earned his Ph.D. in EECS from MIT (2014), an M.S.E. from Princeton (2009), and a B.Tech. from IIT Delhi (2007). His papers have been cited over 23,300 times, and he is a member of the Halls of Fame of all three premier computer architecture conferences — MICRO, HPCA, and ISCA. He was a recipient of the “Under 40 Innovators Award” at DAC in 2025, and won the 2026 ACM SIGARCH Maurice Wilkes Award.

His research is funded by NSF, DARPA, IARPA, SRC (JUMP 2.0), the Department of Energy, Intel, Google, Meta, Qualcomm and TSMC. He serves as Co-Director of the Center for Research into Novel Computing Hierarchies (CRNCH) and co-chairs the Chakra Execution Traces & Benchmarks working group within MLCommons. He served as Program Vice-Chair for ISCA 2023 and Program Co-Chair for MICRO 2026.

Ph.D. · 2014

MIT

Electrical Engineering & Computer Science

M.S.E. · 2009

Princeton

Electrical Engineering

B.Tech. · 2007

IIT Delhi

Electrical Engineering (Honors)

Research Interests

The directions used to organize and tag the full publication list.

AI/ML Accelerators Compositional & Cognitive AI Distributed AI Systems Efficient LLM & Model Inference AI-Assisted Design Interconnection & On-Chip Networks Simulation & Benchmarking Emerging Tech & Packaging Memory & Virtual-Memory Systems Edge & Embodied Computing Privacy & Security
Browse publications by these topics →

Released Tools

Open-source simulators and frameworks from the Synergy Lab.

Distributed AI Systems
ASTRA-simDistributed AI/ML systems simulator
ChakraAI/ML execution traces (MLCommons)
AI Accelerators
SCALE-simSystolic-array simulator
MAESTROAI accelerator dataflow cost model
STONNECycle-accurate flexible AI accelerator simulator
FEATHERReconfigurable AI accelerator RTL + compiler
Networks-on-Chip
Garnet 2.0Network-on-chip model in gem5
OpenSMARTSingle-cycle multi-hop NoC generator

Professional Service

Conference Organization
Program Co-Chair — MICRO 2026
Program Vice-Chair — ISCA 2023
Artifacts Evaluation Co-Chair — HPCA 2022
General Chair — NOCS 2021
Tutorials & Workshops Chair — ISPASS 2021
Program Co-Chair — NOCS 2020
Co-Chair — RISC-A 2019
Special Sessions Co-Chair — NOCS 2019
Co-Chair — RISC-A 2018 (Inaugural)
Publicity Co-Chair — NOCS 2018
Student Travel Grants Co-Chair — PACT 2018
Student Travel Grants Co-Chair — ISCA 2017
Tutorials & Workshops Chair — ASPLOS 2016
Technical Program Committee
IEEE Micro Top Picks 2026
HPCA 2026
MICRO 2025
ASPLOS 2025
IEEE Micro Top Picks 2025
ISCA 2025
MLSys 2025
Rising Stars in MLSystems 2025
MICRO 2024
ISCA 2024
MLSys 2024
MICRO 2023
IEEE Micro Top Picks 2023
MLSys 2023
ASPLOS 2023
DATE 2023 · topic co-chair
MICRO 2022
SC 2022
MLSys 2022
IEEE Micro Top Picks 2022
HPCA 2022
DATE 2022 · topic co-chair
MICRO 2021
ISCA 2021
ISCAS 2021
DATE 2021 · topic co-chair
HPCA 2021
MICRO 2020
ISCA 2020
IEEE Micro Top Picks 2020
DATE 2020
Hot Interconnects 2019
MICRO 2019
PACT 2019
ISCA 2019
DAC 2019 · track chair
DATE 2019
AISTECS 2019
MICRO 2018
DAC 2018
IPDPS 2018
ISPASS 2018
DATE 2018
DAC 2017
DATE 2017
MICRO 2016
Hot Interconnects 2016
DAC 2016